Document Type : Original Article

Authors

• Shahbaz Reyhani ¹
• Sina Khalaji-Zadeh ²

¹ University of Guilan

² Department of Electrical Engineering, University of Guilan

Abstract

This paper presents a high-performance digital low-dropout (DLDO) regulator employing a hybrid control architecture based on a successive approximation register (SAR) and an up–down counter. The proposed design enhances transient response and output voltage stability by combining the fast convergence capability of the SAR with the fine regulation of the counter. In the proposed architecture, three comparators with upper and lower threshold levels around the reference voltage are used in place of a single comparator to accurately detect output-voltage deviations from the allowable range. In addition, a binary-to-thermometer decoder is utilized to reduce switching-induced voltage fluctuations, thereby improving output voltage ripple performance.

The proposed DLDO is implemented in a 180-nm CMOS technology and operates over an input voltage range of 0.8–1.8 V, providing an output voltage range of 0.6–1.6 V. It supports a load current range from 2.5 mA to 50 mA at a clock frequency of 20 MHz. The proposed regulator achieves a settling time of less than 150 ns, a line regulation of 15 mV/V, and a load regulation of 1.018 mV/mA. Furthermore, it exhibits a high current efficiency of 99.89% with a quiescent current of 51.7 µA, while occupying an active area of 0.044 mm² and requiring only a 10 pF output capacitor. The achieved figure of merit (FoM) of 0.0752 ps demonstrates the effectiveness of the proposed design for fast and efficient voltage regulation in modern integrated systems.

Keywords

• Digital Low-Dropout regulator
• Successive Approximation Register
• Up–Down counter
• System on Chip